(A) Field of the Invention
The present invention relates to a power supply circuit for a semiconductor integrated circuit and, more specifically, to a power supply circuit having a voltage controller for controlling the supply voltage inside the integrated circuit.
(B) Description of the Related Art
A constant voltage of the power source is generally requested in an integrated circuit consuming a large load current at a low supply voltage. FIG. 1 shows a conventional arrangement of an integrated circuit and an associated power source. The integrated circuit includes a lead frame 11 having a source terminal 12 and a ground terminal 14 formed on the lead frame 11, across which is connected a voltage source 51 which supplies a voltage required by the integrated circuit. The lead frame 11 includes an island 52 mounting thereon a pellet or chip 16 having a source pad 17 and a ground pad 18, which are connected with the lead terminals 12 and 14, respectively, by bonding wires 21.
The pellet 16 also mounts thereon circuit blocks 36 to 40, which are fed with electric power from a source line 22 and a ground line 23 connected with the pads 17 and 18, respectively. The connection between the source terminal 12 and the source pad 17 through the bonding wire 21 involves a parasitic resistance because of the contact resistance therebetween. The source line 22, which is formed by a metal wire, also involves a parasitic resistance. A parasitic resistance is also involved in the ground terminal 14, ground pad 18, bonding wire 21 and ground line 13.
A power supply to the integrated circuit 11 shown in FIG. 1 is effected by applying a constant voltage from the voltage source 51 across the lead terminals 12 and 14.
A problem arises with the conventional integrated circuit in that a desired supply voltage cannot be secured for the integrated circuit when a large load current flows through the integrated circuit at a low supply voltage. This is because the influence of the parasitic resistance becomes significant as the load current increases, lowering the source potential and raising the ground potential.
An improved integrated circuit is also known which includes an increased number of source pads to reduce the parasitic resistance as involved in the source line and ground line to stabilize the source voltage of the integrated circuit, as described in JP-A-6(1994)-163700, for example.
FIG. 2 shows the improved integrated circuit, which has an internal circuit 107 in the central part of a rectangular substrate, a plurality of source pads P1, P2 and P3 disposed adjacent to respective sides S1, S2 and S3 of the substrate and connected together by an in-package wiring 108 to an external source terminal 106. A functional circuit 104 is disposed adjacent to the top side S1 of the substrate to activate the internal circuit 107. The functional circuit 104 is connected to the source pad P1 by a metallic film wiring L1 formed on the substrate and also connected to the source pad P2 on the left side S2 by a metallic film wiring L2. Another functional circuit 105 is disposed adjacent to the bottom side S4, and connected to the source pad P2 by a metallic film wiring L3 and to the source pad P3 by a metallic film wiring L4. A metallic film wiring L5 provides a connection between the source pads P1 and P3.
It will be noted that each of the wirings L1, L2, L3, L4 and L5 is associated with a corresponding parasitic resistance R1, R2, R3, R4 and R5. The parasitic resistance of the metallic film wiring between the functional circuit 105 and the combination of source pads P2 and P3 connected to the external terminal 106 through the in-package wiring 108 is a parallel resistance formed by parasitic resistances R3 and R4 of the wiring L3 and L4.
Assuming that the source pads P2 and P3 were not provided, the functional circuit 105 is fed with electric power from only the source pad P1, and the resulting parasitic resistance involved in the functional circuit would be a parallel resistance of the series parasitic resistances R1, R2 and R3 and the series resistance of parasitic resistances R4 and R5. Thus it will be seen that the resultant parasitic resistance would be significantly larger compared to that when the source pads P2 and P3 are provided. The provision of an increased number of source pads thus reduces the parasitic resistance involved in the wiring, and hence a voltage drop, thereby stabilizing the supply voltage applied to the integrated circuit.
A problem with the improved integrated circuit resides in the fact that if the integrated circuit requests a large load current at a low supply voltage, there must be provided a large number of source pads, with the consequence that an increased area of the substrate must be allotted to the source pads, resulting in an increased size of the integrated circuit.